Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
NVIDIA · US CA Santa Clara · listed 42 days ago
SeniorEngineering (other)
As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on…
Read the full description
Free registration — your contact details plus five quick fields about the role you want, or your CV — unlocks every description on the site, plus the apply link.
- The complete posting, as the employer wrote it
- Apply directly on NVIDIA's own site
- A match score on every job, from your profile or your CV